The present invention relates to a technique of generating a physical layout for an integrated circuit being designed.
In the past, an integrated circuit was normally designed with respective regions where p- and n-channel transistors should be placed (which will be herein called xe2x80x9cp- and n-channel transistor regionsxe2x80x9d) separated from each other to satisfy a constraint involved with the actual fabrication process of the circuit. This is because a relatively wide isolation region had to be provided between p- and n-wells. In that case, the total area of circuit elements to be laid out could be rather small and the generation of a parasitic thyristor could also be avoided.
However, the isolation region between the p- an d n-wells tends to decrease its required area thanks to recent development of new well isolation techniques such as trench isolations. Also, since a substrate with low resistance is now available, the generation of the parasitic thyristor is avoidable even if no such isolation regions are provided. Furthermore, as for a transistor with a silicon-on-insulator (SOI) structure, the doped regions of the transistor function as isolation regions by themselves and yet the parasitic thyristor can be eliminated, too.
Considering these developments of the fabrication technologies, the conventional layout that provides the isolation region between the p- and n-channel transistor regions now might have some downsides. For example, the wires might be overly complicated or the occupied areas and delays caused might both be greater than a layout without the isolation region. Accordingly, a layout, in which p- and n-channel transistors are both placed in a single region, would be preferred to reduce the area required.
Nevertheless, almost no such layout structures or methods have been proposed yet. For example, James B. Kuo and Ker-Wei Su disclosed an exemplary layout for an inverter with an SOI structure (see xe2x80x9cCMOS VLSI Engineering Silicon-on-Insulator (SOI)xe2x80x9d, Chapter 3, p. 72, Kluwer Academic Publishers). However, no one has ever reported any structure or method for generating a physical layout for a general-purpose circuit efficiently by taking advantage of the features of the SOI structure.
It is therefore an object of the present invention to provide structure and method for obtaining a layout more efficiently by making full use of the recent developments of fabrication technologies.
In a CMOS circuit, a switching circuit made up of p-channel transistors and a switching circuit made up of n-channel transistors (which will be herein called xe2x80x9cp- and n-channel transistor circuitsxe2x80x9d, respectively) perform binary operations in such a manner that one of these two circuits is the dual of the other. Accordingly, in designing a layout structure for the CMOS circuit, the p- and n-channel transistor circuits may be represented as dual transistor connection structures (i.e., graphic structures) and a resultant dual graph may be drawn on a graphic plane. In this manner, a best layout structure with simplified wires can be obtained. And this is the basic concept of the present invention.
Specifically, an inventive layout structure for an integrated circuit includes a pair of p- and n-channel transistors placed closely to each other. As the structure is viewed from above, a direction in which a wire connected to the source or drain of the p-channel transistor extends is substantially vertical to a direction in which a wire connected to the source or drain of the n-channel transistor extends.
According to the present invention, a physical layout for an integrated circuit being designed can be obtained efficiently. In addition, wires can be placed in a single interconnection layer over the transistors without having the wires make any unwanted detour.
Another inventive layout structure for an integrated circuit includes a pair of p- and n-channel transistors placed closely to each other. The transistors in the pair are placed so that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, respectively, the wires can be extended substantially vertically to each other as the structure is viewed from above.
According to the present invention, a physical layout for an integrated circuit being designed can be obtained efficiently. In addition, wires can be placed in a single interconnection layer over the transistors without having the wires make any unwanted detour.
Still another inventive layout structure for an integrated circuit includes a pair of p- and n-channel transistors placed closely to each other. The pair of transistors includes five terminals. And one of the five terminals is a gate terminal connected to the respective gates of the p- and n-channel transistors.
Thus, the present invention provides a structure effectively applicable to a basic cell for a gate array.
An inventive method for generating a layout for a CMOS circuit being designed includes the steps of: selecting a pair of p- and n-channel transistors out of multiple transistors of the CMOS circuit and regarding the pair of transistors as a layout unit, where one of the p- and n-channel transistors in the pair is the dual of the other; and placing the pair of transistors so that the transistors are located closely to each other and that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, respectively, the wires can be extended substantially vertically to each other as the structure is viewed from above.
An inventive system for generating a layout for a CMOS circuit being designed includes: means for plotting planar graphs for a circuit made up of p-channel transistors and a circuit made up of n-channel transistors, the two circuits together making the CMOS circuit; means for grouping the p- and n-channel transistors, included in these two circuits, into multiple pairs of p- and n-channel transistors using the planar graphs so that each said pair of transistors is used as a layout unit and that one of the transistors in each said pair is the dual of the other; means for initially placing each said pair of p- and n-channel transistors to meet a relative positional relationship as defined by the planar graphs so that the p- and n-channel transistors are located closely to each other and that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, respectively, the wires can be extended substantially vertically to each other as the structure is viewed from above; means for optimizing the placement of each said pair of transistors so that an overlap between the p- and n-channel transistors is eliminated and that the p- and n-channel transistors connected together are even closer to each other; and means for interconnecting together terminals of the pairs of transistors placed.
Another inventive system for generating a layout for a CMOS circuit being designed uses a gate array, in which multiple basic cells are arranged in columns and rows. Each said basic cell includes a pair of p- and n-channel transistors placed closely to each other so that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, respectively, the wires can be extended substantially vertically to each other as the structure is viewed from above. The system includes: means for plotting planar graphs for a circuit made up of p-channel transistors and a circuit made up of n-channel transistors, the two circuits together making the CMOS circuit; means for grouping the p- and n-channel transistors, included in these two circuits, into multiple pairs of p- and n-channel transistors using the planar graphs so that each said pair of transistors is used as a layout unit and that one of the transistors in each said pair is the dual of the other; means for initially assigning each said pair of p- and n-channel transistors to associated one of the basic cells in the gate array to meet a relative positional relationship as defined by the planar graphs; means for optimizing the assignment of the pairs of transistors according to an index such as area or total wire length; and means for interconnecting together terminals of the pairs of transistors placed.